As B-ISDN is prevalent, the large-scale ATM switches will be more required. Moreover, they should have the novel architectural features-modular architecture, scalability, and cost-effectiveness-in order to be practical. The modularity of ATM switch architecture makes it easy to be implemented with Pin-Limited Chips(PLCs), and the scalability and the cost-effectiveness make the switch economical.
In this thesis, we propose a switch architecture, called as the Bypass switch which is of space-division type and uses output queueing. It has the modularity and the good scalability. It consists of a switch network and many output buffers. The switch network consists of a series of stages comprising our own switching modules. Between adjacent stages, switching modules are shuffleinterconnected and there are interconnection links to output buffers. The Bypass switch uses the partial rerouting algorithm and employs the auxiliary bypass links, which enable it to be more cost-effective. The architectures of switching modules and output buffers are designed, too.
We estimate the performance by simulation and analyze the number of PLCs required to implement the Bypass switch. Comparing the Bypass switch with Tandem Banyan network, we show that our architecture of the size 1024×1024 requires PLCs about 40% less than Tandem Banyan network under uniform traffic condition at full load to attain $10^{-6}$ cell loss probability. We also show that the Bypass switch have better characteristics than other current ATM switches.
