The needs for high-speed floating point computation have been growing more and more. Just a few years ago, due to the high cost of floating point hardwares, FPU used to be employed as a separate optional coprocessor of personal computer systems. But the need of FPU as a necessary part of CPU and the improvement of fine semi-conductor technologies has made it possible to integrate it on a single chip microprocessor. This paper deals with the design of FPU which is compatible to intel 80486 microprocessor npx(numeric processor extension) systems. The point is area-optimized and efficient implementation of data path for high speed floating point computations.