Porous silicon was discovered in 1950's by Turner and Uhlir during the electropolishing silicon wafer in HF solution. Although porous silicon can find its possibility of application in diverse area, it has not been used commercially since the pore formation mechanism and the properties of porous silicon are not completely understood and the process technology is not mature.
The purpose of this study is to investigate the effect of process condition on the pore size distribution in porous silicon, which can be used in capacitor structure of DRAM device which has been highly integrated. Porous silicon was prepared by the anodic reaction using n-type and p-type silicon wafers as anode and platinum as cathode in mixed solution of HF and ethanol in a teflon reactor. Its structure and pore size were examined by SEM photographs. Porous silicons formed on p-type silicon wafer show the network structure of fine pores of which diameters are less than 10nm. Porous silicons formed by anodization in 1:1 HF/ethanol solutions on n-type silicon have the trench structure and their pore diameters are found in the range of 500-700Å when the applied current is 80mA. Pore diameter is increased up to about 1000Å, by chemical etching in $HF-HNO_3-H_2O$ mixed solution with n-type porous silicons.
The electric field distribution at the interface was calculated by solving the Poisson's equation. The magnitude of the field around the pore tip, which determines the tunneling current, is much greater than that on the pore wall. Because of the difference in the field strength, pores on n-type silicon propagate straight down. Effects of the depletion layer thickness on the spacing between the pores are also discussed.