The i486 microprocessor includes five stage pipeline with an integrated 8-Kbyte cache. A variety of techniques associated only with RISC processor are used to execute the average instruction in 1.8 clocks. And most of frequently used instructions are executed in one clock cycle. The design of an efficient scheme is required to satisfy this specification, due to the requirement of complete compatibility of K486 processor with the i486 processor. The prefetch unit and the decoder unit are most important in this respect. Therefore prefetch, decode scheme and logic level circuits for fundamental operations, and more detailed schemes for jump instruction are given in this paper.
