A RT(register transfer)-level design of a 32bit microprocessor for 2-D graphics operations is carried out in this thesis. VHDL simulation was performed to verify the proposed design. In defining the instruction set of the proposed RISC microprocessor, program statistics of PostScript interpreter was used. This microprocessor has an ALU, comparator, and 32bit barrel shifter to process data and 2Kbyte direct-mapped on-chip instruction cache for fast instruction fetch. It has a register file which has 32 general purpose registers and 3 internal buses. The proposed RISC microprocessor is expected to operate at 25MHz(it uses 4-phase non-overlapped clocking scheme.) using 1.6μm CMOS technology. In order to complete one instruction in one cycle, a 4-stage pipeline is used.
