서지주요정보
DCT 고속 알고리즘의 하드웨어 구현을 위한 성능 개선 및 설계에 관한 연구 = A study on the performance improvement and design for hardware implementation of fast DCT algorithm
서명 / 저자 DCT 고속 알고리즘의 하드웨어 구현을 위한 성능 개선 및 설계에 관한 연구 = A study on the performance improvement and design for hardware implementation of fast DCT algorithm / 전준현.
저자명 전준현 ; Jeon, Joon-Hyeon
발행사항 [서울 : 한국과학기술원, 1986].
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등록번호

4103865

소장위치/청구기호

학술문화관(문화관) 보존서고

MEE 8655

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초록정보

When we transmit digital image data, we can considerably compress the transmission bandwidth by reducing the redundancy of image data. Among the kind of methods called "source coding", the data compression by orthogonal transformation has better performance than DPCM from the view point of low bit rate. The objective of this research is the hardware realization of DCT of which performance is comparable to KLT, which is the optimum-transform data compression among many kinds of transformational methods. DCT hardware realization becomes possible with many new algorithms which have been proposed so far. Chen's algorithm suggesting a method for DCT systematically decomposing the transformation matrix into several matrix is one of the most well-known, but a recently published Lee's algorithm using the FFT is much simpler to realize even though its performance is more or less inferior to Chen's. If we can obtain performance approximately equal to that of Chen's by improving the DCT hardware realization by Lee's, this will be very advantageous. In this paper, many performance improving methods for DCT hardware realization are proposed and applied to Chen's and Lee's algorithm to compare the performance. As a result, Lee's algorithm turns out never to be inferior to Chen's algorithm. Based on this improvement was designed a multi-stage DCT processor for pipeline/parallel processing. A simulation has been performed using the proposed FDCT processor for the 1.544Mbps digital coder which is capable of transmitting image signal via 1.544Mbps channel. There is no visual degradation in 1.544Mbps coder using the proposed FDCT with respect to that using real FDCT. The resulting system shows good picture quality at rates above 0.3 bpp. * Mbps = Mega bit per sec bpp = bit per pel (:pel = picture element)

서지기타정보

서지기타정보
청구기호 {MEE 8655
형태사항 [iii], 102 p. : 삽도 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Joon-Hyeon Jeon
지도교수의 한글표기 : 김재균
지도교수의 영문표기 : Jae-Kyoon Kim
학위논문 학위논문(석사) - 한국과학기술원 : 전기및전자공학과,
서지주기 참고문헌 : p. 97-100
주제 Image compression.
Delta modulation.
Computer algorithms.
고속 fourier 변환. --과학기술용어시소러스
DPCM. --과학기술용어시소러스
화상 압축. --과학기술용어시소러스
고속 알고리듬. --과학기술용어시소러스
Image transmission.
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