When we transmit digital image data, we can considerably compress the transmission bandwidth by reducing the redundancy of image data. Among the kind of methods called "source coding", the data compression by orthogonal transformation has better performance than DPCM from the view point of low bit rate.
The objective of this research is the hardware realization of DCT of which performance is comparable to KLT, which is the optimum-transform data compression among many kinds of transformational methods. DCT hardware realization becomes possible with many new algorithms which have been proposed so far. Chen's algorithm suggesting a method for DCT systematically decomposing the transformation matrix into several matrix is one of the most well-known, but a recently published Lee's algorithm using the FFT is much simpler to realize even though its performance is more or less inferior to Chen's. If we can obtain performance approximately equal to that of Chen's by improving the DCT hardware realization by Lee's, this will be very advantageous.
In this paper, many performance improving methods for DCT hardware realization are proposed and applied to Chen's and Lee's algorithm to compare the performance. As a result, Lee's algorithm turns out never to be inferior to Chen's algorithm. Based on this improvement was designed a multi-stage DCT processor for pipeline/parallel processing.
A simulation has been performed using the proposed FDCT processor for the 1.544Mbps digital coder which is capable of transmitting image signal via 1.544Mbps channel. There is no visual degradation in 1.544Mbps coder using the proposed FDCT with respect to that using real FDCT. The resulting system shows good picture quality at rates above 0.3 bpp.
* Mbps = Mega bit per sec
bpp = bit per pel (:pel = picture element)