"Software breadboarding" replacing the costly conventional breadboarding is an essential step for logically complex and densely packed VLSI circuitry. Thus, TOP-DOWN design method should become an very attractive approach to the Design-Automation process in recently VLSI CAD systems. Support for TOP-DOWN method includes a development of software design tool, especially at functional level.
In this thesis a TRANSLATOR. vl is presented as a support design tool for TOP-DOWN process which transform high level representations in AHPL(A Hardware Programming Language) into microprograms ready for loading into microprogram ROM.
Also, a complete design of the SORT-PROCESSOR is presented as an example of functional level systematic design.