Inability to scale down the threshold voltage of CMOS transistors due to sub-threshold leakage concerns, coupled with continuous dimension scaling has aggravated dynamic power density of modern microprocessors.The resulting heat density limits the operating frequency of microprocessors, giving room to dynamic voltage and frequency scaling (DVFS).DVFS is effective in reducing both the dynamic and leakage power consumption, preemptively when temperature rises beyond limits, and opportunistically to save energy when microprocessors are lightly loaded.
When applied to on-chip cache memories, however, voltage scaling is limited to a minimum voltage, called VCCMIN.Scaling the supply voltage below VCCMIN surpasses the noise margins of many SRAM cells, rendering them unreliable. This problem owes to inherent artifacts or nanoscale fabrication, known as process variations. Thus, process variations either limit reliability or low power operation.
To ensure reliable cache operation below VCCMIN, a fault tolerant mechanism is inevitable. This dissertation reviews such fault-tolerant caches design which exploit various within-cache and extra-cache redundancies. It then presents two novel techniques, fault buffers and Macho, which provide variation-resilience in small L1 caches and larger L2 caches, respectively. Fault buffers belong to the class of extra-cache redundancies which substitute for faulty words only, in a word-accessed L1 cache. A fully-associative design of fault buffers minimizes area overhead, a banked-approach limits latency and access energies while a DVFS-controlled power-gating infrastructure curtails leakage power by disabling underused banks.
The second technique, Macho, emulates a trade-off between cache capacity and low-power by presenting a within-cache word substitution technique. "Macho" stands for a "Model-oriented and Adaptive Cache Organization". One of the main contribution is the development of a rigorous closed-form reliability model of word substitution caches, with the help of Fault Tree Models and Collision Graph Models. The results serve as starting point of design-space exploration when the mathematics is simplified using logarithmic scale under proper limits. The model suggests the grouping of multiple cache sets to form a Logical modules (LM) which are implemented non-intrusively on top the conventional cache architecture. Although resilient, the performance and energy saving largely depends upon Logical Module Configuration. Given the spread of random fault distribution, two configuration algorithms are presented, along with a mechanism to selectively employ one of them, based upon LM`s local fault density. This approach provides algorithmic resilience and energy savvy operation over a wide DVFS range.
CMOS의 전력소모는 고집적회로 설계를 어렵게 하는 제한요소이다. 마이크로프로세서의 파워소모를 줄이기 위한 가장 효율적인 방법 중 하나는 처리할 작업량에 따라 시스템의 전압과 클럭주파수를 조정하는 전압/클럭주파수 스케일링 (DVFS)이다. 하지만 SRAM으로 구성된 캐시로 인하여 전압 스케일링이 VCCMIN 수준으로 제한된다. 그 이유는 이러한 캐시 메모리가 VCCMIN 이하의 공급전압에서는 안정적으로 동작하지 못하기 때문이다. 본 논문에서는 VCCMIN이하의 공급전압에서도 정상 동작이 가능한 새로운 형태의 캐시 구조를 제안한다. 첫 번째 고장감내 캐시구조는 고장난 캐시 위치의 데이터를 저장하는 Fault buffer(FB)를 사용한다. 두 번째 캐시 구조는 "Macho"라 불리는 모델기반 적응형 캐시구조로써 워드단위의 고장 감내성을 제공한다. "Macho"는 캐시블록의 고장난 캐시워드 위치에 저장되는 데이터를 다른 희생(sacrificial) 캐시블록의 워드 위치에 저장한다. 구현과 동작의 단순성으로 인해 "Fault buffer"는 작은 규모 (L1), “Macho”는 큰 규모 (L2 또는 Last-level) 캐시의 동적 전압 및 클럭주파수 스케일링에 사용되기에 매우 매력적인 캐시 구조이다.
