Two implementation issues for a distributed LR-WPAN device, specified for a 2.4GHz ZigBee application, have been introduced.
The first issue is the reduction of frequency settling time of a frequency synthesizer, which dominates the excessive active time duration for TDD switching between Tx-mode and Rx-mode and for the channel switching. In stead of adapting or widening the loop-bandwidth of the synthesizer, a two-point channel control architecture has been proposed to achieve short settling time even with an integer-N synthesizer, which has relatively narrow bandwidth and low active power consumption compared to a fractional-N one. The two-point channel control scheme is composed of main-path and compensation-path controls. While the main-path is the same as that of a conventional PLL, a DAC with tunable gain is used to directly control the linearized VCO for the compensation-path. We have achieved the settling time of near zero sec for the maximum 75MHz frequency jumping from 2.4GHz, which is specified by the standard, with the use of an integer-N architecture with narrow 20kHz loop-bandwidth. In addition, the fast-settling synthesizer has utilized a Vertical-NPN parasitic transistor, which is available in a conventional triple-well CMOS process, for the 1/f noise sensitive VCO biasing, and thereby the close-in phase-noise performance can be improved. Compared to the case of MOS transistor biasing, the close-in phase-noise was improved by 5dB with the same active power consumption. For the high frequency divider circuits, a low-voltage modified-TSPC circuit topology with only 2-transistor stacks has been proposed. By adapting the modified-TSPC topology for the high-frequency divider circuits, under lowered supply voltage of 1.2V, the power consumption was significantly reduced. When the phase-noise at 1MHz offset from 2.4GHz output frequency is -116.6 dBc/Hz, the total power consumption of the fast-settling synthesizer using 0.18㎛ CMOS technology is only 4.2mW. The simultaneous reductions of both frequency settling time and active power consumption have been achieved by adapting the two-point channel control scheme to an power-efficient integer-N synthesizer architecture.
The second, a radio architecture with fast analog frequency Offset Cancelation Loop (OCL) has been presented for the 2.4GHz ZigBee application. The OCL is comprised of a low-IF receiver, a fractional-N frequency synthesizer and a phase-domain frequency offset detector. The Offset Detector (OD) is based on a Frequency/Phase Detector (PFD) and Time-to-Digital Converters (TDC). Because the OCL uses a phase-domain OD, a stability concern is essentially needed to be practically used. The dependency of the OCL stability on the PLL parameters was analyzed from the frequency domain equivalent model. As a result, we have achieved both a strong stability and a fast offset cancellation speed that matches the PLL locking time, by adapting the PLL loop-gain linearly. Additionally, a trade-off relationship between the OCL accuracy and hardware complexity was discussed and a practical design example with a non-uniform Time-to-Digital Convertor (TDC) has been shown for the 2.4GHz ZigBee specification. For the 0.18㎛ CMOS process, the OCL takes less than 30㎲ to reject the offset frequency of 298976 eng
Two implementation issues for a distributed LR-WPAN device, specified for a 2.4GHz ZigBee application, have been introduced.
The first issue is the reduction of frequency settling time of a frequency synthesizer, which dominates the excessive active time duration for TDD switching between Tx-mode and Rx-mode and for the channel switching. In stead of adapting or widening the loop-bandwidth of the synthesizer, a two-point channel control architecture has been proposed to achieve short settling time even with an integer-N synthesizer, which has relatively narrow bandwidth and low active power consumption compared to a fractional-N one. The two-point channel control scheme is composed of main-path and compensation-path controls. While the main-path is the same as that of a conventional PLL, a DAC with tunable gain is used to directly control the linearized VCO for the compensation-path. We have achieved the settling time of near zero sec for the maximum 75MHz frequency jumping from 2.4GHz, which is specified by the standard, with the use of an integer-N architecture with narrow 20kHz loop-bandwidth. In addition, the fast-settling synthesizer has utilized a Vertical-NPN parasitic transistor, which is available in a conventional triple-well CMOS process, for the 1/f noise sensitive VCO biasing, and thereby the close-in phase-noise performance can be improved. Compared to the case of MOS transistor biasing, the close-in phase-noise was improved by 5dB with the same active power consumption. For the high frequency divider circuits, a low-voltage modified-TSPC circuit topology with only 2-transistor stacks has been proposed. By adapting the modified-TSPC topology for the high-frequency divider circuits, under lowered supply voltage of 1.2V, the power consumption was significantly reduced. When the phase-noise at 1MHz offset from 2.4GHz output frequency is -116.6 dBc/Hz, the total power consumption of the fast-settling synthesizer using 0.18㎛ CMOS technology is only 4.2mW. The simultaneous reductions of both frequency settling time and active power consumption have been achieved by adapting the two-point channel control scheme to an power-efficient integer-N synthesizer architecture.
The second, a radio architecture with fast analog frequency Offset Cancelation Loop (OCL) has been presented for the 2.4GHz ZigBee application. The OCL is comprised of a low-IF receiver, a fractional-N frequency synthesizer and a phase-domain frequency offset detector. The Offset Detector (OD) is based on a Frequency/Phase Detector (PFD) and Time-to-Digital Converters (TDC). Because the OCL uses a phase-domain OD, a stability concern is essentially needed to be practically used. The dependency of the OCL stability on the PLL parameters was analyzed from the frequency domain equivalent model. As a result, we have achieved both a strong stability and a fast offset cancellation speed that matches the PLL locking time, by adapting the PLL loop-gain linearly. Additionally, a trade-off relationship between the OCL accuracy and hardware complexity was discussed and a practical design example with a non-uniform Time-to-Digital Convertor (TDC) has been shown for the 2.4GHz ZigBee specification. For the 0.18㎛ CMOS process, the OCL takes less than 30㎲ to reject the offset frequency of +200kHz from the 2.475GHz nominal carrier frequency, within the accuracy of $\pm$5ppm.
본 논문에서는 LR-WPAN 등 네트워크 단말기의 구현에 있어 이슈가 되고 있는 두가지 문제점에 대한 해결 방안을 2.4GHz ZigBee 응용을 예로써 소개하였다. 전반부에서는 고에너지 효율을 갖는 무선단말 구현에 있어서 지속적인 화두가 되고 있는 저전력 회로구현과 함께 송/수신기 간의 전환시간을 획기적으로 줄일 수 있도록 하는 빠른 settling time의 주파수 합성기 구조에 대하여 논하였으며, 후반부에서는 저가 무선단말 구현의 예로써 수신기의 frequency offset을 빠른 시간에 제거 할 수 있으면서도 구현 복잡도가 낮은 회로구성에 대하여 논하였다.
첫째로, 고에너지 효율을 갖는 무선단말기 구현을 위해, 본 논문에서는 제안된 two-point 채널 컨트롤 방법을 전력효율이 우수한 integer-N 주파수 합성기 구조에 기타 저전력 회로기술을 이용하여 적용시킴으로써, 빠른 주파수 settling time과 저전력 소모를 동시에 얻을 수 있음을 실험적으로 보였다. 빠른 settling time을 얻기 위하여, 전력효율이 나쁜 fractional-N 합성기에 기반한 광대역 주파수 합성기를 사용하는 대신에, 제안된 two-point 채널 컨트롤 방법은 저전력 integer-N 합성기에 저주파 통과 특성의 main-path와 고주파 통과 특성의 compensation-path롤 결합하여 저전력 광대역 통과 특성을 갖도록 구성되었다. PVT 변화에 의해 발생할 수 있는 두 path간의 부정합을 보상하기 위해서는 선형화된 VCO와 선형적인 이득제어가 가능한 DAC를 compensation-path 내에 채택 함으로써, compensation-path 주파수 tuning이 선형적으로 제어 가능 하도록 하였다. 0.18㎛ CMOS 공정을 이용하여 제작된 2.4GHz ZigBee 주파수 합성기의 실험결과, ZigBee 표준에서 명시하고 있는 최대 주파수 변화에 대해서 실험장비의 resolution내에서 이상적인 near zero settling time을 얻을 수 있었다. 또한, 1/f noise에 민감한 VCO의 close-in phase noise를 줄이기 위하여 CMOS 공정에서 구현 가능한 Vertical-NPN (VNPN) bipolar transistor를 VCO의 current source transistor로 이용 함으로써, MOS bias 경우에 비해서 약 5dB의 noise성능 개선을 얻을 수 있었다. 기타 저전력 회로설계 기술로는 전력소모가 상대적으로 많은 고주파 prescaler 회로에 기존의 3단 transistor stack의 TSPC topology를 수정하여 저전압 하에서도 고속동작이 가능케 하는 2단 stack의 modified-TSPC구조를 제안하였다. 이를 이용하여 구성된 1.2V 주파수 합성기의 실험결과, 약 4.2mW의 극소전력만을 소모하면서 1MHz offset에서 -116.6dBc/Hz의 phase-noise 성능을 얻을 수 있었다.
두번째로, 저가 무선단말을 구현하는데 있어 반드시 해결해야 하는 문제인 여러 부정합 등을 보상하는 방법의 하나로써, 2.4GHz ZigBee 응용을 예로 수신기 frequency offset을 빠른 속도로 제거 할 수 있는 Offset Cancellation Loop (OCL)를 제안하고 이의 안정성을 분석 검증하였으며, 최종적으로 회로복잡도가 낮은 OCL의 구현 예를 보였다. 제안된 OCL은 low-IF 수신기, fractional-N 주파수 합성기, 그리고 phase-domain frequency Offset Detector (OD)로 구성되어 있으며, OD에서 검출된 frequency offset을 직접 fractional-N 주파수 합성기의 $\Sigma\Delta$-modulator에 연속적으로 feedback 시킴으로써 빠른 제거속도를 갖도록 하였다. Offset 제거 속도 향상을 위해 채택된 phase-domain OD를 제안된 OCL에 사용하기 위해서 선행되어야 하는 안정도 분석과 함께, 주파수 합성기 구성 parameter들의 안정도에 대한 의존도를 분석하여 큰 frequency offset 처리능력과 함께 열악한 PVT-variation 하에서도 안정적인 동작을 가능케 하는 회로방법을 보였다. 또한, OCL의 정확도와 회로복잡도간의 trade-off 관계 분석을 통해 낮은 복잡도의 non-uniform resolution을 가지는 Time-to-Digital Converter (TDC)에 기반한 OD 회로구조를 설계 예로써 보였다. 0.18㎛ CMOS 공정을 이용하여 제안된 OCL을 구성 하였으며, ZigBee 단말기에서 수신 가능한 최대 frequency offset인 $\pm$198.4kHz 보다 큰 +200kHz의 offset을 가정했을 때 약 30㎲ 이내의 시간에서 주어진 offset을 $\pm$5ppm의 정확도 이내로 제거 가능함을 보였다.
