서지주요정보
Optimal datapath design considering deep submicron interconnects = 심층 서브마이크론 인터커넥트를 고려한 데이타 경로 최적화
서명 / 저자 Optimal datapath design considering deep submicron interconnects = 심층 서브마이크론 인터커넥트를 고려한 데이타 경로 최적화 / Joon-Seo Yim.
저자명 Yim, Joon-Seo ; 임준서
발행사항 [대전 : 한국과학기술원, 1998].
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8009232

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DEE 98054

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초록정보

For the high-speed, low power consumption, and small silicon area, the datapath has been designed by full custom approach in the commodity microprocessor chip. As the design complexity increases, the datapath compiler which generates the compact layout has been used both for ASIC and cost-performance microprocessor design to improve the design productivity. In this thesis, the new approaches and algorithms for the high-performance datapath compiler are proposed: such as placement, buffer sizing, interconnect design, track assignment, and layout schemes. To examine the performance of these approaches, 'real-world' examples from the several complex microprocessors are used for the experiment. In determining the optimal datapath placement a hybrid approach of genetic algorithm(GA) and simulated annealing(SA)is applied to minimize both the track density and the wire length. To improve the computation speed, we utilize the good initial population generation heuristics and datapath-specific genetic operators. Experimental results show that our hybrid approach outperforms the existing genetic approaches and gives similar results to the simulated annealing using only 44% of the computation time of SA. The traditional datapath compiler generates the same-sized buffers for all bits. Considering the bit-by-bit difference of load capacitance in real designs, the bit-wise buffer sizing scheme is proposed. This scheme leads to the balance of the bit-wise delay and the power minimization. According to the experiments, the power consumption of the tri-state driver for the long running bus can be minimized as much as 43% by the bit-wise buffer sizing scheme. As the CMOS technology enters into deep submicron design era, the inter-wire cross-coupling effect gives large impact on the performance. The iterative interconnect sizing method considering the cross-coupling effect is suggested with experimental data based on 0.25μm technology. An effective control signal ordering scheme considering the cross-coupling effect minimizes the power consumption by 10% and the delay by 15%. A new track assignment algorithm considering the switching behavior based on the evolutionary programming is proposed to minimize the cross-coupling effect. Using these effective interconnect methodologies, we can improve the chip performance by 40%. Finally, three layout schemes, two dimensional transistor placement, the vertical ploy positioning, and the micro-level floorplan mixing the regular and irregular bit cell, are proposed for the compact module generation and easy technology migration. Using these schemes, we can improve the datapath compactness by 30% compared to the traditional datapath compiler.

서지기타정보

서지기타정보
청구기호 {DEE 98054
형태사항 xi, 128 p. : 삽도 ; 26 cm
언어 영어
일반주기 저자명의 한글표기 : 임준서
지도교수의 영문표기 : Chong-Min Kyung
지도교수의 한글표기 : 경종민
수록잡지명 : "Datapath Layout Optimisation using Genetic Algorithm and Simulated Annealing". IEE Proceeding, Computers and Digital Techniques. An Institution of Electrical Engineers Publication, vol. 145, no. 2, pp. 135-142 (1998)
학위논문 학위논문(박사) - 한국과학기술원 : 전기및전자공학과,
서지주기 Reference : p. 110-117
주제 Datapath
Interconnect
Deep submicron
Microprocessor
CAD
데이타패쓰
인터커넥트
심층 서브마이크론
마이크로프로세서
캐드
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