A spread spectrum modem is designed in this thesis work. Direct sequence spread spectrum algorithm is implemented using field programmable gate arrays(FPGAs) and an embedded microprocessor, 80C186EC which controls the entire modem system.
The modulation method used in this work is DQPSK for noncoherent demodulation at the receiver. For the fast code acquisition required in time division duplex mode, a pseudo noise matched filter is used. Processing gain of the modem is programmable up to 64. It is easy to modify the system to have a higher processing gain because the matched filter has cascadable structure. Frequency offset is detected symbol-by-symbol by a frequency discriminator. The frequency offset is compensated by a complex sine multiplier. For fast complex multiplication, we use fast SRAM for look up table.
A synchronous or an asynchronous data terminal equipment(DTE) can be attached to this modem. All data is synchronously transferred through a channel in a high level data link control(HDLC) frame. The HDLC frame is placed in an assigned time slot for the TDD. Full duplexing is also achieved by using different pseudo noise(PN) sequences.
As a result, the modem receiver implemented in this work can detect the data well at 38.4kbps or above with the matched filtering and frequency drift compensation algorithm in the laboratory test.
