The implementation of a single-chip, low noise CMOS PLL frequency synthesizer for wireless communication applications has been presented. The circuit is composed of three main components, i.e., a Voltage-Controlled Oscillator (VCO), 1 / 7, 8 dual-modulus prescaler and a Phase-Frequency Detector (PFD). The circuit is fully integrated with the exception of the loop filter components in a standard digital 0.8㎛ CMOS process. To be immune to noise, all the circuits in the synthesizer use the differential schemes and the digital parts are designed by the static one.
A new high speed low noise VCO with precise signal swing control has been proposed. While the VCO output frequency can be controlled by the current of the each delay cell, each of the maximum and the minimum voltage levels can be controlled precisely by the respective reference voltage. Since this overhead circuit does not increase the output load, we succeed to obtain VCO operating in GHz range. With this method, the output swing levels are controllable independently of the power supply and the ground and thus a level shifter and an amplifier are not needed.
Another new high frequency ring oscillator suitable for multi-phase clock generation has been proposed. The ring oscillator consists of inverters with negative delay elements that are derived from the other nodes in the ring oscillator circuit. In this way, it is possible to obtain the cell delay of the ring oscillator which is smaller than the fundamental inverter delay. Simulations show that the resulting operating frequencies can be twice as high as those obtainable in the conventional approaches. A new VCO combined with the new ring oscillator has been also studied. Simulation shows that the 25% higher operating frequency can be obtained compared with the conventional approach.
A new D flip-flop with a single clock, differential static scheme for a dual-modulus prescaler has also been proposed. The maximum operating frequency of 1.45GHz was achieved and the output jitter of the proposed scheme was 35% less than that of the true-single phase clocking approach. A new D flip-flop in dead-zone free PFD was also proposed.
CMOS monolithic PLL frequency synthesizer incorporating above new features has been fabricated using 0.8㎛ single poly and double metal process. The fabricated VCO shows a center frequency of 800MHz and the tuning range of 25%. The supply sensitivity of the VCO free-running frequency is 2.3%/V, and the temperature coefficient of that is 1200ppm/℃. The measured frequency synthesizer performance has a locking range of 700MHz to 1GHz with -80dBc/Hz phase noise at a 100KHz carrier offset. The test chip has an active area of 0.34㎟ and consumes 125mW at maximum frequency from a 5V supply. Our result shows the feasibility of a monolithic CMOS PLL frequency synthesizer suitable for mobile communication in scaled down CMOS technologies.
