A frequency synthesizer is designed and implemented by using PLL (Phase-Locked Loop) at S-band(2.225 ~ 2.23GHz) with 160kHz steps. This system consists of a reference oscillator, a phase detector, a loop filter, a VCO(Voltage-Controlled Oscillator), and a frequency divider. In this thesis VCO and a loop filter are designed and fabricated, and one-chip PLL IC(Fujitu, MB1508) including a phase detector and a frequency divider(a dual-modulus prescaler) is used. VCO using a high-Q dielectric resonator yields 10dBm output power and a flat frequency response of 5.15MHz/V gain. The frequency stability of the frequency synthesizer is less than 0.5ppm. Output power of that is about 7dBm.