서지주요정보
K486 마이크로프로세서 설계를 위한 정량적인 검증방법 = Verification of K486 microprocessor : a quantitative approach
서명 / 저자 K486 마이크로프로세서 설계를 위한 정량적인 검증방법 = Verification of K486 microprocessor : a quantitative approach / 박창재.
저자명 박창재 ; Park, Chang-Jae
발행사항 [대전 : 한국과학기술원, 1996].
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소장정보

등록번호

8006247

소장위치/청구기호

학술문화관(문화관) 보존서고

MEE 96032

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초록정보

As the design complexity increases along with the improvement of semiconductor integration technology, an efficient design flow and verification strategy is crucial to the success of the design project. A new quantitative design flow and verification methodology based on profile and chronology for K486 microprocessors is suggested in this thesis. In microprocessor design, most of time is consumed in the verification efforts to validate the design. The behavioral and structural design are verified using the high level language, C to speed up the simulation time, while the gate-level design is verified using hardware description language Verilog-XL. The consistency between each models is confirmed with the help of IPC(InterProcess Communication) and piggybacking method. The signal flow graph is used for the justification of signal integrity and the correct translation of C level model into hardware level model. For the complete software compatibility with i486, real application programs are used in board-level simulation. To increase the confidence level of test, verification coverage concept and bug life time model are introduced. Using these quantitative verification concept, we can design and verify the CISC microprocessor successfully in a rather shorter design time compared with conventional design flow.

서지기타정보

서지기타정보
청구기호 {MEE 96032
형태사항 vi, 63 p. : 삽도 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Chang-Jae Park
지도교수의 한글표기 : 경종민
지도교수의 영문표기 : Jong-Min Kyung
학위논문 학위논문(석사) - 한국과학기술원 : 전기및전자공학과,
서지주기 참고문헌 : p. 62-63
주제 K486 마이크로프로세서
설계 검증
K486 microprocessor
Design verification
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