Very Large Scale Integrated (VLSI) circuits require a structured and hierachical design methodology to cope with design complexity. Automated synthesis from the functional description of the control logic allows decrease of design time while keeping logical correctness. However, computer-aided synthesis of control logic often yields a circuit requiring a large implementation area. Therefore, automated synthesis of VLSI system must include area optimization procedures. In this thesis, two area optimization techniques for control logic synthesis are addressed.
Finite State Machine (FSM) play a major role in the control part of the VLSI system. FSM is constructed in two main ways; two-level implementation (PLA) and multi- level implementation such as standard cell implementation. The implementation area of FSM heavily depends on the state encoding. In chapter 2, a new efficient state encoding algorithm was proposed and implemented as a computer program, SECH (State Encoding by Construction of Hypercube). SECH is applicable for both two-level and multi-level implementation by controlling the encoding affinity.
The state encoding process is modelled as a construction of hypercube, where the code of each state is given by the coordinate of the corresponding vertex of the NE- dimensional hypercube, where NE is the number of encoding bits. Experimental results show that SECH produces better results than existing two-level specialized state encoding programs and multi-level specialized state encoding programs in the reduced CPU time.
The ability to shorten development cycle has made Field-Programmable Gate Arrays (FPGAs) attractive compared to standard cell implementation. One important class of FPGAs are those that use lookup tables (LUTs). The ability of an m-input LUT to implement any Boolean function of less than m variables differentiates the synthesis of LUT circuits from the conventional logic synthesis. The optimization goal for LUT-based FPGA synthesis is typically the minimization of the total number of used LUTs.
In chapter 3, a new optimization algorithm for LUT-based FPGA is presented and implemented. Decomposition of a Boolean network is formulated as an algebraic cofactoring, and the technology mapping is performed by algebraic cofactor packing. Experimental results show that the proposed algorithm decomposes infeasible nodes in a shorter CPU time with reduced number of nodes than existing methods. It shows 11% improvement over cube packing, 10% improvement over disjoint decomposition, and more than 24% improvement over algebraic factorization, respectively. Implementation of the algorithm on top of misII shows favorable results compared with mis-pga_new.
To implement the optimized network in a real FPGA chip, the interfacing program between the proposed logic optimizer and commercially available placement and routing program was implemented. After the placement and routing process, the number of CLBs for the network optimized by proposed technology mapping system is less than the one for the network optimized by commercial technology mapping program.
