This thesis describes the high-level design of a 32-bit RISC microprocessor core. Verilog simulation was performed to verify the proposed design. In designing the proposed RISC microprocessor core, the GRIMDOL, that was designed in VLSI Systems Lab. KAIST in 1993, was used as a basis. This RISC microprocessor core has 54 instructions, an execution unit, a control unit, and an instruction fetch unit. And an execution unit includes an ALU, a 32-bit funnel shifter, a multiplier & divide step register, and 32 general purpose registers to process data. In order to complete one instruction in one cycle, a 5-stage pipeline is used. We expect that this RISC core with additional peripheral logic, can be used as a controller and a microprocessor in many application systems.
