서지주요정보
플라즈마 화학증착법에 의해 제조된 기억소자용 고유전 탄탈륨 산화박막에 관한 연구 = PECVD $Ta_2O_5$ dielectric thin films for memory devices
서명 / 저자 플라즈마 화학증착법에 의해 제조된 기억소자용 고유전 탄탈륨 산화박막에 관한 연구 = PECVD $Ta_2O_5$ dielectric thin films for memory devices / 김일.
발행사항 [대전 : 한국과학기술원, 1995].
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소장정보

등록번호

8005697

소장위치/청구기호

학술문화관(문화관) 보존서고

DEM 95004

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리뷰정보

초록정보

High quality tantalum oxide ($Ta_2O_5$) thin film was prepared by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD) for high density dynamic random access memory (DRAM) device. The microstructure and composition of the tantalum oxide thin films and the growth of interfacial silicon oxide layer were investigated. And they were related to the electrical characteristics of the film. The $Ta_2O_5$ thin films with a thickness of 14nm were deposited at 95℃ and annealed at various temperatures (700℃~850℃) in $O_2$ and $N_2$ ambients. Annealing in an $O_2$ ambient led to a high dielectric constant $(ε_r(Ta_2O_5)=24)$ as well as a small leakage current $(E_BD=2.3MV/cm)$, which were due to the improved stoichiometry and the decreased impurity carbon content. Annealing in an $N_2$ ambient resulted in poor and nonuniform leakage current characteristics. The as-deposited $Ta_2O_5$ films were crystallized into $δ-Ta_2O_5$ phase after annealing at above 750℃ regardless of the ambient. The leakage current of the film abruptly increased after annealing at 850℃ probably because of the stress caused by thermal expansion or constriction. Thin $Ta_2O_5$ films were deposited on Si substrates at the temperature range of 145℃~205℃, and the effects of deposition temperature on electrical properties of the $Ta_2O_5$ films were studied. Interfacial silicon oxide layer under the $Ta_2O_5$ film was formed at the early stage of $Ta_2O_5$ deposition. The silicon oxide affected greatly the electrical properties of total dielectric film in case of the very thin $Ta_2O_5$ film. Therefore the effect of silicon oxide should be considered to investigate the electrical properties of the $Ta_2O_5$ thin films. The increase of the deposition temperature improved the electrical properties of $Ta_2O_5$ films due to improved the stoichiometry. The $Ta_2O_5$ film deposited at 205℃ by ECR-PECVD was amorphous and had $Co/C_Ta$ of 2.4 which was slightly different from that of the prefect $Ta_2O_5$. The $Ta_2O_5$ film deposited at 205℃ showed excellent electrical properties: $E_BD=4.4MV/cm$, $ε_r(Ta_2O_5)=25$ and $J<1Ⅹ10^{-9}A/㎠$ at 2.5 Volt. The film deposited at 205℃ which showed excellent electrical properties was annealed at various temperatures in an oxygen ambient. The electrical properties of the film could not be improved by annealing in an oxygen ambient at high temperatures due to the crystallization of the $Ta_2O_5$ film and the growth of the interfacial silicon oxide layer. The growth of the interfacial silicon oxide layer was observed by using a high resolution transmission electron microscope (TEM) and its effects on the electrical properties of the dielectric film were also studied. Very thin $Ta_2O_5$ film could be an effective diffusion barrier of the oxidant during the annealing because the diffusion rate of oxidant was very slow in the $Ta_2O_5$ film ($D_Ta205/D_SIO2=0.18$ at 850℃). Bottom electrodes of Pt, TiN and W have been evaluated for use with $Ta_2O_5$ films deposited ECR-PECVD. The oxidation of bottom electrode surfaces during the $Ta_2O_5$ film deposition and the effect of the oxides on the capacitance of the $Ta_2O_5$ film were studied. Incubation time for the $Ta_2O_5$ film deposition depended on the oxidation of the substrates. Incubation time of the W substrate, which is apt to make oxide, had longer by 3 min than that of the Pt substrate. The oxidation of the substrates was ended at the very early stage of $Ta_2O_5$ deposition regardless of the $Ta_2O_5$ film deposition time. The ratio of thickness and dielectric constant $(d/(nm)/ε_r)$ of the interfacial oxides were 0.231 and 0.576 at TiN and W substrates respectively. Which were much smaller than the ratio of 0.921 at Si substrate. The $SiO_2$ equivalent thickness of the interfacial oxide were 0.9nm and, 2.1nm at TiN and W substrates respectively. These values show the limitation of the substrates as a lower electrode used for DRAM. By using of the Pt low electrode, which has not interfacial oxide, capacitance of 30 fF was possible at as small as 0.8μ㎡ electrode area. Utilizing the anti-oxidation lower electrode material with the very thin ECR-PECVD $Ta_2O_5$ film of excellent electrical properties is very promising approach to developing low-power high-density DRAM's beyond 64 Mb.

서지기타정보

서지기타정보
청구기호 {DEM 95004
형태사항 vi, 136 p. : 삽화 ; 26 cm
언어 한국어
일반주기 저자명의 영문표기 : Il Kim
지도교수의 한글표기 : 천성순
지도교수의 영문표기 : Soung-Soon Chun
학위논문 학위논문(박사) - 한국과학기술원 : 전자재료공학과,
서지주기 참고문헌 : p. 125-131
주제 Plasma-enhanced chemical vapor deposition.
Thin films.
Dielectrics.
화학 증착. --과학기술용어시소러스
유전체. --과학기술용어시소러스
유전체 박막. --과학기술용어시소러스
Ferroelectric storage cells.
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