The large computational requirements and the massively parallel architecture of neural networks have led to a number of hardware implementations.
In this thesis, we describe an implementation of the spoken digit recognition system using VLSI neural network chip; Universally Reconstructable Artificial Neural-network (URAN) chip developed by Korea Telecom.
The spoken digit recognition system consists of a PC/AT host computer, a DSP board for speech data acquisition and feature extraction, and a prototype neural board including the URAN chip. The URAN chip operates in analog-digital mixed mode, and consists of a decoder and four modules of synapse cells. Each module provides 8 inputs and 8 outputs to yield 8x8 synapse cells. The neural network board consists of two URAN chips, three 32 kbyte SRAMs for storing weight values to be downloaded to URAN chip every 10ms speech frame. two 10,000 gates Field-Programmable Gate Array (FPGA) chips for implementing off-chip digital logic, data converters (A/Ds and D/As), and integrators for cummulating the output current of synapse cells. One FPGA chip contains circuits for interfacing to the host computer, and for generating the pulse stream to be applied to the inputs of synapse cells. Another FPGA chip includes 16 pairs of adders and registers for calculating weighted-sum of inputs to neurons. The output function of neurons is carried out on the DSP board. All operations in the neural network board are done in about 800 clock cycles.
