Due to the rapid growth of VLSI technology in the last decade, the CPU performance is significantly increased. As a result, the performance gap between CPU and I/O subsystem has been increased, and thus the I/O subsystem becomes a bottleneck of the system. Furthermore, the performance of a multiprocessor system is more dependent on the efficiency of IOP than the other subsystems because IOP executes all I/O commands exclusively.
In this paper, we identify bottlenecks in the IOP architecture by simulation studies, and propose architectural enhancements to alleviate those bottlenecks. For this purpose, we develop a trace-driven simulator. The simulation target system is the TICOM that is developed as a main system of the NAIS(National Administration Information System). As a workload of the simulator, we uses real traces extracted from the Multimax whose architecture is similar to TICOM's.