Performance of the communication network plays an important role in determining the overall performance of multicomputers. Hardware routers which interconnect processing elements can greatly improve the performance of the communication network by overlapping the computation and the communication.
In this thesis, we propose a hardware router for recursive circulant multicomputers. The proposed hardware router is based on wormhole switching and a minimal/deterministic routing. We use two virtual channels per physical channel in order to prevent deadlocks which may be caused by the adopted routing algorithm. We decouple input and output timing in order to reduce the propagation delay within the proposed hardware router. And we partition the data path into smaller routing modules for the router to be scalable. Thus it is only necessary for routing modules to be cascaded in order to construct a high-degree hardware router. Moreover, we can construct a hardware router of low hardware complexity and simplicity by this modular design.
The proposed hardware router is implemented and verified using VHDL. Simulation results show that a channel bandwidth becomes 10MBytes per second with a 30MHz clock. In the case of recursive circulant G($2^5,4$), the required hardware complexity is 50% lower than a router architecture using crossbar switches, the message latency is saturated 5% earlier, and the maximum network throughput is 2% lower. Thus the proposed hardware router is cost-effective compared with a router architecture using crossbar switches.
