In this thesis, we propose a new 2-dimensional FIR filter using a time-division multiplier. The proposed architecturre has three characteristics. First, we maintain merits of CSD multiplier suitable for high speed system[16-19]. Because CSD approximates a filter coefficient, its performance, hardware complexity and processing speed, is superior to those of others. Second, we can find a solution to a problem of CSD, degradation of filtering performance caused by approximation of filter coefficients. Finally, we can reduce a word length in a processing element of systolic architecture by introducing a time-division multiplication method. When the systolic array is implemented in VLSI, the word length is related to chip area. By the proposed method, filter coefficients are partitioned into most significant and least significant parts. And multiplication is performed in the different time interval. Although multiplication result is not available in a processing element, we can obtain complete filtering output at the last processing element. We can obtain optimum time-division number for hardware complexity by the proposed algorithm. The proposed filter is implemented in EPLD for the purpose of testing the logic and will be applied to HDTV system.
