Most recent microprocessors require powerful floating-point processing unit(FPU) as a standard option. This paper describes the design of a datapath for pipelined FPU satisfying IEEE standard 754. A two-phase non-overlapping clock scheme is used, with cycle time of 30n sec. This FPU adopts a RISC approach to meet the clock requirement of 33MHz. The designed FPU can produce a result of basic instructions such as add, sub and multiply every clock in the pipelined mode. The latency for basic instruction is 3. The designed FPU achieves a speedup of about two when compared with an HK387 which is pin-to-pin compatible with 80387. The designed datapath was written in verilog HDL.
