The emphasis of this thesis is totally focused on the improvement of the GaAs FECFET device characteristics, especially the gate parasitic capacitance lowering by undercut-etching both the gate sides.
A FECFET is fabricated. It's S-parameters are measured for the extraction of small signal equivalent circuit parameters and the noise parameter modeling.
Isolation etching of the device in chemical etchant is subject to the intrusion of etchant through the void edge, which leads to the reduction of the effective gate width. This is turned out to be the major reason why Idss and gm decreases after the chemical etching was done.
Undercut-etching of gate edges with the void passivated by PR and the drain/source metal edges protected by $SiN_x$ film results in the reduction of gate parasitic capacitances. The etching is done by $NH_4OH$ etchant system.
For the undercut etched FECFET, $f_T$ extracted based on the equivalent circuit parameters increases from 13GHz to 24.2GHz and 16.2GHz to 26.9GHz for the device of $L_g$=2.8㎛ and $L_g$=1.7㎛, respectively.
From the Podell noise model which takes $C_gd$ term into account, it is figured out that the minimum noise figure, $F_min$, decays by 1dB at $f_T$=12GHz (Where the gate length is 1.7㎛ and drain source current $I_ds$ is 100% $I_dss$)
