In this thesis a digital data processor in mobile communication system composed of encoder and decoder is designed, and implemented using FPGA's. The encoder encodes the data to minimize error which can be occured in channel, constructs digital data stream, and transmits them. The decoder receives digital data stream, regenerates bit clock and using this bit clock, recovers data, and does channel decoding. Advanced Mobile Phone Service System, which are being serviced, employs a 20K baud digital signaling to provide information needed in the various stages of call setup and control. A new hardware implementation method which are suitable for integrated circuit is proposed. The designed architecture and the detail explanation of implemented hardware including BCH encoder/decoder, WBD encoder/decoder are given. This design firstly verified via digital simulation. Finally to verify their operation in real hardware system, We implement the design using FPGA's. The functionality of FPGA's are extensively verified under our own designed testing environment employing IBM PC.
