Microarchitecure with multiple pipelined functional units supporting parallel execution of instructions is able to achieve significant performance enhancement through instruction-level parallelism. Various methods such as out-of-order execution, branch prediction and register renaming have been used to maximize the instruction-level parallelism. In using these schemes, however, a recovery mechanism for handling exception and branch misprediction must be provided. In this thesis, we propose and verify a new hardware scheme supporting precise exception handling for out-of-order execution and prompt recovery mechanism from branch misprediction. The proposed hardware consists of CARF(Content-Addressable Register File) and IB(In-order Buffer), where the CARF is realized as CAM(Content Addressable Memory) and a simple datapath and the IB is realized as circular buffer. CARF differs from general register file where the positions of registers are fixed within it. In the CARF, registers are assigned and relocated on the appropriate position during their life-time and eliminated from it at the expiry of their life-time. The life-time of a register is the minimum duration for which the register needs to exist in the register file for the correct execution of the given program. Previous solutions for precise exception handling for out-of-order execution require separate spaces for both sequential state according to in-order program execution and out-of-order state according to out-of-order program execution, which require complex datapath and hardware resource for exception recovery. The salient feature of the proposed scheme in this dissertation is that the in-order state and the out-of-order state for out-of-order execution model are included in a single space called CARF, which enable prompt and precise exception handling. And, it also provides a very efficient means for register renaming. Moreover, the recovery time from branch misprediction in the proposed architecture is faster than previous schemes. Instruction set simulator for a dataflow architecture supporting out-of-order execution was developed to verify the operation of the proposed architecture for several benchmarks including 24 Lawrence Livermore loops and recursive programs.
