Space charge limited current (SCLC) measurement and field effect analysis are plausible as diagnostics for the amorphous silicon thin film transistor (a-Si:H TFT) production lines. The SCLC in planar $n^+in^+$ devices were characterized by computer simulation and experiments. New field effect analysis method for a-Si:H TFT was proposed and verified through simulation and experiments, and was applied to measure the density of states after artificial stresses on TFT's. The SCLC's in a-Si:H sandwich and planar structures were investigated. Channel length dependence of SCLC is explained by the effective Fermi level modulation between the $n^+$ layers, and the current in a long channel ($L>1\mu m$) is enhanced by the high field near the drain electrode as well as SCLC, e.g. Frenkel-Poole mechanism. Even though the planar $n^+in^+$ structure experiences surface state effects in addition to the high field effects, it was shown that it can be used for the measurement of the density of states (DOS) near Fermi level. From SCLC measurement, the DOS of a-Si:H near Fermi level was found to be about $1 \times 10^{16} /cm^3 eV$, and the characteristic energy of deep states was 89 meV. To apply field effect analysis to TFT's with really thin semiconductor layers, the back surface effect on the transfer characteristics was estimated by computer simulations and verified by experiment. It turned out that the proposed field effect analysis method is rather insensitive to the choice of the flat band voltage and gives reliable result. From this field effect analysis the characteristic energy of the tail states was 24-26 meV, where this value is quite close to the results from other experimental methods, e.g. time-of-flight measurements. New field effect analysis method was applied to measure the DOS of bias stressed a-Si:H TFT's and light soaked a-Si:H TFT's. Positive gate bias stresses give little DOS changes in the upward region over Fermi level, but the charge trapping in the gate insulator makes the threshold voltage shift. Negative gate bias stresses yield apparent increase of DOS around Fermi level, which was estimated to be $1 \times 100^{18}/cm^ 3eV$ under the bias stress of -70 volts for 1000sec. Light soaking under AM1 for 4 hours increased DOS by $4 \times 10^{17} /cm^3 eV$ around Fermi level.
