For high speed image processing applications, fast access of image data is inevitable. Most of image processing operations access image points in regular patterns, which include horizontal line, vertical line, block, forward diagonal and backward diagonal. There have been extensive researches in designing memory system to enable simultaneous access of these image patterns. Previous researches are classified in two categories : memory systems using a row rotation and memory systems using a linear transformation. The row rotation schemes require complex modulo operation on the prime number. On the contrary, the linear transformation schemes use simple XOR gates. Consequently, it is desirable to use the linear transformation schemes in high speed image processing applications.
In this thesis, we propose a parallel memory system using a linear transformation for high speed image processing. To overcome the conflicts in arbitrary access of image points, we modify the memory module assignment method to use double of memory modules necessary. We also design a new address calculation circuit and a routing circuit suitable for the linear transformation. The functionality of designed system is verified by simulation using a logic simulator, Verilog-XL. Compared to a previous system using row rotation, proposed system has better performance in processing time without lots of additional hardware circuits.
