A Direct Coupled FET Logic inverter is designed and fabricated using Floated Electron Channel Field Effect Transistor(FECFET) as unit device. It consists of 2 FECFET's of which gate lengths are all 2$\mu$m. One is the enhancement-mode FECFET(switching FET) and has channel length of 42$\mu$m. The other is depletionmode FECFET (load FET), 6$\mu$m channel length. DC transfer characteristics of the fabricated DCFL inverter showes very high transfer gain and large noise margin. With supply voltage of $V_{DD}$ = 1V, the transfer gain is 7.5 and the calculated noise margin is 0.18V from maximum square definition. AC performance measurement is carried out by contacting the microprobes directly to the wafer pads. Each pad is connected to $V_{DD}$, ground, pulse generator, oscilloscope, respectively, through coaxial lines Inverted output pulse is observed when 1 MHz input pulse is given. Due to the high input capacitance(16pF) of the oscilloscope, inverted output showes long rising and falling time. The uniformity of the MOCVD grown layer thickness and the reproducibility of the mask($SiO_2$) patternning are the key points to a large integration of FECFET circuits.
