An analog neural network circuit for high density integration is introduced. It's prototype chip is designed in 3 by 3 ㎟ die. It uses only one MOSFET to implement a synapse. The number of synapses per neuron can be expanded by parallel chip connection. The influence of nonlinearity in synapses is analyzed. A formalization of the back propagation which can be applied to this circuit is shown. Some simulation results are shown and disscussed.