The data compression techniques by motion estimation and compensation are used in many HDTV and video codec systems to reduce the temporal redundancy in image sequences. Until now, many researches have been devoted to the development of efficient motion estimation algorithm, and consequently, various algorithms have been produced. In HD-MAC system, symmetric block matching algorithm is used for motion estimation. This algorithm estimates the motion vectors such that the MCI(Motion Compensated Interpolation) errors are minimized. In VLSI realization aspect, the symmetric block matching algorithm has some problems.
This thesis describes some method for VLSI realization of symmetric block matching algorithm. In order to solve the problems, which occur in the VLSI realization of symmetric algorithm, two methods are proposed and compared. This thesis, also, presents an systolic architecture for symmetric algorithm and simulation results.
