In the radar target detection, the ordered-statistics(OS) constant false alarm rate(CFAR) processor has been known to have small CFAR loss in detection performance relative to the cell-averaging(CA) CFAR processor in homogeneous environments and much less performance degradation in nonhomogeneous environments compared with that in homogeneous environments. So it is desirable to use the OS-CFAR processor in radar detection. However, it is generally difficult to do the OS-CFAR detection in real-time with general-purpose computers or digital signal processors because of the high throughput rate required in radar systems. Recently, a few systolic architectures for the OS-CFAR processor have been proposed for real-time processing of the OS-CFAR detection.
In this thesis, a new systolic architecture for the OS-CFAR processor is proposed. In the proposed architecture, each processing element (PE) can compare two reference data cells with one test cell simultaneouly in each clock cycle. So the utilization of each PE in the proposed architecture is 100% whereas the utilization of each PE in the systolic architecture previously reported by Ritcey and Hwang is 50% because of one clock delay between two adjacent PE's active in computation. This can speed up the data processing rate by a factor of two. Using the proposed systolic architecture, we obtain the reduced number of communication with the one proposed by Ritcey and Hwang. Using the proposed PE's we obtain the efficient systolic architecture for the CA-CFAR processor, too. Actual implementation of a PE in integrated circuits needs further study.
