An efficient hardware architecture for implementing programmable stack filters is proposed. In the realization binary stack filters are implemented following the bit serial approach, which is one of the most efficient algorithms for stack filters, and then the gray-level output is obtained from the binary outputs. Here by including control coefficients in binary stack filtering representation, programmable binary stack filters are realized. In addition, pipelied architectures are employed to improve the speed. The performance of the proposed realization is examined through logic simulations with the Daisy system and circuit simulations with the SPICE. The results indicate that by using approximately 50,000 transistors any stack filter of span 9 with clock frequency 41MHz can be realized.
