Graphics hardware has been a challenging area of a research and development. New hardware architectures are continually being developed to cope with the ever increasing demands of computer graphics cost/performance. Graphics processor is one of the results of those needs and several processors have been proposed.
In this thesis, we present a new graphics processor in the framework of the raster scan frame buffer graphics. Graphics primitive operations are decomposed into atomic RISC-type instructions that can be implemented using a simple and fast hardware architecture. We propose a instruction set and special graphics hardware features in addition to RISC core.
Comparing to the other architectures it marks less than or equal cycle times for primitive graphics operations. And by simulation, we show that proposed architecture works correctly.
