This thesis describes the architecture and design of a Graphics Processor for as medium-resolution graphics system.
The structure of Graphics Processor(GP) is composed of a host interface, Graphics CPU, drawing accelerator(DA), CRT controller, and memory controller. This GP, requring no external support logic, outputs RGB signals at a 20-MHz pixel rate and directly controls a bit-map video RAM (VRAM) memory array. Pixels stored in the 1k X 1k bit map can be any of 16 colors. This system can be directly interfaced to commercial microprocessors. Graphics CPU have 14 instructions and can directly be programmed using high-level graphics commands.
The GP achieves a maximum drawing speed of 2.5 million pixels/sec. This system is implemented using 9 EPLD's(model number EPM5128 from ALTERA), with SRAM and buffers.
