In this thesis, a hardware accelerator for the Korean Character generation from the control point set of Bezier curve expressed as a 3rd order polynomial in X and Y was designed for implementation as gate array chip. The chip consists of four major parts; FIFO, loader, Bezier curve generator, and output handler. The Bezier curve generator contains six bit-serial pipelined multipliers and tens of adders for computing the Bezier curve, operating in a parallel and pipelined manner. All the internal operations are performed bit-serial, while external communications are done bit-parallel. Around 15,000 gates were used to implement all of the above mentioned functions in a 50K gate array chip. Simulation results have shown the correct functioning of the chip up to the operating frequency of 40MHz, which is equivalent to the computation of about two million points per second.
