This thesis is concerned with a new design of a demodulator for V.22bis MODEM using the analytic signal sampling method.
The structure of the demodulator is composed of a Hilbert filter and a decimator, and the Hilbert filter is implemented in the form of an 11th FIR filter. We propose a novel circuit implementation of the Hilbert transformer which is effective in chip area. The proposed circuit which uses the delayed input substractor has definite advantage over the AT&T demodulator in terms of the performance and hardware cost.
The proposed novel demodulator has been verified by circuit simulators such as SWITCAP and SPICE, and successfully implemented using the discrete components. The results show that the performance of our proposed demodulator is very comparable to that of the AT&T with about 50% reduction in chip area.