In this thesis work, a dedicated architecture is proposed for the Viterbi scoring procedure in an HMM-based real-time large-scale isolated word recognition system. The proposed architecture can update every state metric of HMM models up to the vocabulary size of 1000 with the average number of states per word 50 within a 10 ms frame interval, thus achieve a real-time throughput.
Utilization of parallelism and pipelining allows the architecture to execute 5 million instructions per second. Since memory I/O is the major bottleneck in the system, adoption of faster memories or interleaved memories will gear up its operation cycle.
The elimination of obsolete address pins, by exploiting the sequential accesses of data memories and employing some tag bits, cuts down the pin count of the proposed architecture to 70 except for the ground and power pins, which is much smaller than that of the SRI architecture though the proposed one as yet cannot carry out continuous speech recognition.
Functional simulation of the proposed architecure has been done and the log compression and quantization effects due to integer arithmetic operatoins are also investigated.
본 연구에서는 HMM을 이용한 대용량 고립 단어 인식 시스템에서의 Viterbi scoring 과정을 실시간에 구현하기 위한 구조를 제안하였다. Concurrency를 이용함으로써 단어 당 평균 50 state를 갖는 1000 단어의 어휘를 실시간에 처리할 수 있도록 하였다.
메모리 액세스의 유형을 활용하고 tag bit들을 활용함으로써 필요없는 address pin들을 없앰으로써 pin count를 대폭 줄이고 layout 시의 면적도 줄일 수 있도록 하였다.
