This thesis so concerned with the development of the timing verifier for the CMOS VLSI circuits. The timing verifier reports the information of signal propagation paths to user, so that user can use that information to improve circuit performance.
The timing verifier named KASA is composed of three main parts, which are interface module, path searching module and delay calculation module. Interface module reads input files and constructs data structure, path searching module searches the paths and delay calculation module calculates the delay time of paths using distributed slope model. The module parameters for the delay calculation in KASA are generated by an independent module, called MKMODEL.
We also propose the modified DFS algorithm for searching paths and compare its performance with that of conventional DFS algorithm. The accuracy of KASA is extensively compared with SPICE results and found to be within 20%. The timing verifier is verified through computer simulation on a SUN 3/160 computer.
