A new system bus for tightly coupled multiprocessor computer system is presented in this thesis. Many functions for tightly coupled multiprocessors are supplied by the system bus. The split data transfer protocol, multi-cache coherency protocols, fairness arbitration and interrupt transfer protocols for multiprocessor environments are major characteristics of the system bus.
A split data transfer protocol makes that two or more data transfers are concurrently executed. It is good for multiprocessor environments since there are many processors to request a data transfer simultaneously.
The limitation of the bus is the low data transfer bandwidth. The cache memory reduces the average memory access time and data traffic, but occurs the data consistency problem in multiprocessors. The system bus provides some transfer types and status signals for the cache coherency protocols.
The system bus provides a sophisticated interrupt transfer protocols. It dynamically distributes the interrupts occurred in the system and sends the interrupts to the most idle processor in order to balance loads over processors Fairness arbitration is essential in multiprocessor environment because good load balance over the processors promise good performance. The system bus provides a fairness arbitration algorithm.
After explaining the general characteristics of the system bus for tightly coupled multiprocessor computer system, a new system bus is introduced. Results of simulations are presented which demonstrate that the performance of the system bus is better than those of VMEbus and $Futurebus+.
