Ground bounce and noise in digital circuit boards using high speed CMOS IC are measured and modeled. The dependence of ground bounce and noise on several parameters such as MOS channel length and interconnection wire inductance is investigated, and the optimum output buffer MOS size to achieve small noise generation and fast rise/fall time is proposed. Also it is measured and theoretically proved that there is an unavoidable temporal limit in chip to chip signal propagation. Finally some methods to reduce the noise are investigated.
