200-Gate Metal Gate CMOS Gate Array and Macrocells are designed and fabricated. This Gate Array, named GA1.1, contains 80 Array cells and 34 I/O cells. Gates, latches, flip-flops and a pass transistor logic are defined in Macrocells.
CMOS test patterns are fabricated in order to extract electrical parameters of metal gate CMOS process. 15 stages ring oscillator, 15 stage inverter chain and some other circuits are implemented in GA1.1 base.
The delay time per stage in array cell, which is measured from the ring oscillator and inverter chain, is 14ns.