서지주요정보
Drawing accelerator의 설계 및 제작에 관한 연구 = A study on the design and implementation of drawing accelerator in graphics system
서명 / 저자 Drawing accelerator의 설계 및 제작에 관한 연구 = A study on the design and implementation of drawing accelerator in graphics system / 윤일.
저자명 윤일 ; Yoon, Il
발행사항 [서울 : 한국과학기술원, 1989].
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소장정보

등록번호

4105728

소장위치/청구기호

학술문화관(문화관) 보존서고

MEE 8936

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초록정보

This paper describes the design and implementation of Drawing Accelerator(DA) the architecture of which has not been released in detail. While the DA in graphics controller or graphics system processor performs a few graphics primitives, such as line, circle and arc etc., the proposed DA does more graphic primitives than that of commercial graphics processors with a few additional hardwares. Specifically, the architecture of DA is designed to execute the graphics algorithms concurrently which are implemented by changing some registers with presettable up/down counter data registers. The counters can be operated as adders in the raster-scan graphics system because the coordinates of x- and y-axis are changed by +1, -1 or 0. This architecture in graphics system has the same effects as that with adders of the same number of counters. And the problem of memory bottleneck is reduced by using two-pixel data width. The proposed DA is implemented with EPLD'S AND TTL's, where the coordinate addresses can be generated from 1.25 Mpixels/sec to 3.3 Mpixels/sec at a 10 MHz system clock. The speed limitation is caused by the low speed of EPLS's. If the DA is integrated into one chip, using commercial CMOS technology, the speed of data processing cab be enhanced at least as much as four times.

서지기타정보

서지기타정보
청구기호 {MEE 8936
형태사항 [ii], 66, [2] p. : 삽도 ; 26 cm
언어 한국어
일반주기 부록 : 회로도
저자명의 영문표기 : Il Yoon
지도교수의 한글표기 : 박송배
지도교수의 영문표기 : Song-Bai Park
학위논문 학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과,
서지주기 참고문헌 수록
주제 Computer algorithms.
Metal oxide semiconductors, complementary.
CMOS. --과학기술용어시소러스
컴퓨터 그래픽. --과학기술용어시소러스
컴퓨터 알고리듬. --과학기술용어시소러스
Computer graphics.
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