This paper describes the design and implementation of Drawing Accelerator(DA) the architecture of which has not been released in detail.
While the DA in graphics controller or graphics system processor performs a few graphics primitives, such as line, circle and arc etc., the proposed DA does more graphic primitives than that of commercial graphics processors with a few additional hardwares. Specifically, the architecture of DA is designed to execute the graphics algorithms concurrently which are implemented by changing some registers with presettable up/down counter data registers. The counters can be operated as adders in the raster-scan graphics system because the coordinates of x- and y-axis are changed by +1, -1 or 0. This architecture in graphics system has the same effects as that with adders of the same number of counters. And the problem of memory bottleneck is reduced by using two-pixel data width.
The proposed DA is implemented with EPLD'S AND TTL's, where the coordinate addresses can be generated from 1.25 Mpixels/sec to 3.3 Mpixels/sec at a 10 MHz system clock. The speed limitation is caused by the low speed of EPLS's. If the DA is integrated into one chip, using commercial CMOS technology, the speed of data processing cab be enhanced at least as much as four times.
