Polynomial MOS delay model 을 이용한 스윗치 레벨 논리 시뮬레이터 = Switch level logic simulator using polynomial MOS delay model

• 서명 / 저자: Polynomial MOS delay model 을 이용한 스윗치 레벨 논리 시뮬레이터 = Switch level logic simulator using polynomial MOS delay model / 전기.
• 발행사항: [서울 : 한국과학기술원, 1988].

A new technique is proposed for switch-level logic simulation for NMOS and CMOS logic circuits. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance and the device configuration ratio, the polynomial coefficients being so determined as to best fit the SPICE simulation results for a given fabrication process. This approach can easily and accurately be extended to the case of multiple input transitions. The simulation results show that the proposed method can predict the delay times within 5\% error and with a speed up by a factor of three orders of magnitude for several circuits tested, as compared with the SPICE simulation.

• 형태사항: [iii], 61 p. : 삽화 ; 26 cm
• 언어: 한국어
• 일반주기: 부록 : 1, Input data card. - 2, Input data example ; 저자명의 영문표기 : Ki Jeon ; 지도교수의 한글표기 : 박송배 ; 지도교수의 영문표기 : Song-Bai Park
• 학위논문: 학위논문(석사) - 한국과학기술원 : 전기및전자공학과,
• 서지주기: 참고문헌 : p. 59-61
• 주제: Logic circuits. ; Computer simulation. ; Delay lines. ; MOS 집적회로. --과학기술용어시소러스 ; 논리 시뮬레이션. --과학기술용어시소러스 ; 논리 회로. --과학기술용어시소러스 ; 지연 특성. --과학기술용어시소러스 ; Metal oxide semiconductors.