This paper is concerned with computer simulations for the interface part with the host as well as the generation one of CRT and memory control signals, which are part of the architecture of a graphics display controller NEC PD 7220 whose circuit diagrams are obtained through reverse engineering.
The simulations are performed by using the circuit simulator SPICE and the logic simulator KAISLOG for one half of the overall logic circuits which consists of 13,700 transistors. The interface between the GDC and the host is made flexible by using an asynchronous first-in first-out (FIFO). The generation of CRT control signals plays a fundamental role in a GDC, and they are used to control the entire GDC in combination with the other internal logic circuits while the generation part of memory control signals operates in synchronism with the CRT sync signals. The above-mentioned logic circuits can be used as basic ones in designing any GDC's or graphics processors.
