This paper describes the functional-level design and simulation of the I/O part of a Graphics Processor (GP) which is called OGP (Our Graphics Processor). The I/O part of the OGP consists of Host interface. Screen refresh and CRT timing controller, DRAM refresh controller and Memory controller. Host processor is able to access the GP's local memory indirectly via Host interface. Screen refresh and CRT timing controller generates the HSYNC, VSYNC and BLNK signals to drive the monitor and refreshes the screen periodically. That can be programmed to support the interlace and noninterlace monitor and variable sized video screen. DRAM and VRAM of which GP's local memory consists, are refreshed every refresh interval by DRAM refresh controller. Memory controller generates the VRAM and DRAM control signals and performs several types of memory cycles including DRAM refresh and screen refresh cycle. Plane and Transparency masking to process the pixels and Insertion and Extraction masking to support the bit addressing are also provided.
The simulation of functional behavior of OGP has been done on a silicon compiler, GENESIL.
