In this thesis, a Prolog processor (APP) is designed for high speed execution of Prolog programs, and its preliminary performance is estimated by simulation. APP has a compiler-oriented architecture based on Warren's Abstract Machine, and controlled by horizontal-type microinstructions.
APP consists of a microprogrammed control unit, ALU, and specialized hardware circuits for accelerating unification which is the most fundamental operation in Prolog processing.
The estimated performance is about 270 KLIPS in executing a deterministic "append" program, and the simulation results show that hardwares for accelerating the unification operation greatly improve the overall performance.
