The design, fabrication and performance of a vertical double diffused power MOSFET(VDMOS) are described. The substrate used is antimony (Sb) doped epitaxial wafer. The resistivity of the epitaxial layer is about 10 Ω.cm and the thickness is about 20 ㎛. The channel length which is controlled by sequential p/n+ double diffusion method is about 2-3 ㎛.
To improve the breakdown voltage without degrading the ON-resistance($R_{ON}$), two $p^+$ field limiting rings are laid out around the main pattern. The total chip size is 1150㎛×250㎛. The electrical characteristics of fabricated VDMOS has shown maximum breakdown voltage of about 270 volts, ON-resistance of 110 ohms and the current capability of more than 140 mA for $V_{DS} = 50 volt$, $V_{GS} = 20 volt$.
