This paper concerns with an accurate delay time modeling of the ED MOS logic gates and its application to the multiple delay logic simulator.
The proposed delay model of the ED MOS logic gate takes account of the effects of not only the loading conditions but also the slope of the input waveform. Defining delays as the time spent by the current imbalance of the active inverter to charge and discharge the output load, with respect to physical reference levels, rise and fall mode delay times are obtained in an explicit formulation, using optimized weighting currents at the end points of the voltage transition. The propagation delay times of the transmission gate are precisely analyzed according to two operations modes, that is, synchronous mode and asynchronous mode.
A logic simulator which uses multiple rise/fall delays based on the model as described in the above has been developed.
The new delay model and timing verification method are evaluated with respect to delay time accuracy and execution time.
