An effective technique called Deep Level Transient Spectroscopy (DLTS) for the measurement of deep levels in semiconductor material is reviewed. A DLTS system using a micro-computer is designed and implemented. The system requires a very stable sine wave generator to drive a capacitance meter, i.e., it requires less than ±0.8% variation in amplitude. With this sine wave, we could measure 0.01pF capacitance variation. The system requires only a single scan of about 40 minutes to produce four DLTS signals.
A gold doped p-n-p transistor (2N3468, T.I) has been tested with the system in order to check the performance of the system. $Au^+$ trap in the collector region has been found which is located at 0.34 eV above the valence band edge. The concentration of this trap has been calculated to be about $10^{14}$ atoms/㎤ and the profile of Au was uniform.
Finally, additional specifications for a future system has been recommended based on the experience obtained from this work.
