In this thesis implementation of a very compact and efficient multi-rate vocoder with variable transmission rates of 2.4, 4.8, 9.6 and 15 kbits/s is studied. The overall algorithm of the multi-rate vocoder has been made by slightly modifying the residual-excited linear prediction (RELP) vocoder with the transmission rate of 9.6 kbits/s. The residual encoder employed in the RELP vocoder uses hybrid companding delta modulation (HCDM). This HCDM is used also as a 15 kbits/s coder. If the residual is downsampled before encoding, we can realize a 4.8 kbits/s coder. If the residual encoder is not used, we can realize the system as 2.4 kbits/s coder by incorporating a pitch extractor. In the 4.8 kbits/s coder a pitch predictive loop is used to compensate for the degradation of speech quality due to the downsampling of residual. In a conventional RELP system spectral flattening is done to generate the excitation signal to the synthesizing filter. We have also tested the pitch-implanted residual excitation method to generate the hybrid excitation signal to the synthesizing filter.
Hardware implementation has been carried out in three steps. First the multi-rate vocoder algorithm has been formulated and its parameters has been optimized by real simulation. Second, the algorithm has been tested using 16-bit fixed point arithmetic by integer simulation. Finally, the multi-rate algorithm has been implemented in hardware using bit-slice microprocessors.
Packet switching 등에 의한 통신망에 있어서 음성신호를 부호화하여 전송할 때, channel의 상태 또는 사용자의 수에 따라 전송속도를 적절히 변동시킬 필요가 있다. 그래서 본 논문에서는 2.4 k bits/s 4.8 k bits/s, 9.6 k bits/s, 15 k bits/s 중 어느 전송 속도로든지 전송할 수 있는 시스템을 개발하였다.
본 연구는 크게 나누어 세 단계로 진행되었다. 그 첫단계로서, real simulation 에 의해 algorithm 을 정하고 여러 변수값들의 최적치를 결정하였다. 본 시스템의 algorithm 은 9.6 k RELP 방식을 주축으로하여 가장 간결하고 효율적으로 되게끔 구성하였다. 다음 단계로서, real simulation 에 의해 확정된 algorithm 을 integer simulation 에서 16-bit fixed point 연산을 써서 시험해 보았다. 그결과, 16-bit 연산으로 충분히 hardware implementation 이 가능할 것이라는 결론을 얻었다. 그리하여 마지막 단계로서, 본 시스템의 algorithm 을 micro-program 으로 짜서 bit-slice microprocessor 들과 multiplier, memory 들로 구성된 hardware system에 implementation 하였다.